Enabling reliable low-cost high-capacity flash storage for data centers and hyperscale storage.

Whether you are looking to use an FPGA or an ASIC flash controller to transition to the latest 3D NAND flash memories, our fully scalable and customizable solutions will enable your transition while providing the highest endurance and performance for your storage.

Strongest error correction

Highest error-correction achieved with 10% to 15% gain in RBER under hard-decision decoding.

Lowest Resource Usage & Power

Smallest size and power. Lowest FPGA resource usage in the industry.  

32Gbytes/sec Throughput & Beyond

Achievable throughput by a single instance for ASIC

Best-in-class error-correction performance achieved by FAIDTM core technology

Traditional LDPC solutions require large resource usage and power that scales prohibitively with the ever-increasing throughput requirements, and the issue of error floor prevents them from achieving the required low error-rates without adding complexity.

Using a unique patented technology (finite alphabet iterative decoding) that was invented based on years’ of research by the founding team, our FAIDTM core solutions provide the strongest error-correction capability with highly scalable throughputs and no occurrence of error floor.

Error-correction Performance for 3D QLC NAND
FER vs RBER plot generated from FPGA simulation

Our FAIDTM Value Proposition

We provide custom designed proprietary FAIDTM LDPC IP cores with technical consulting, development and support services that achieve


Can support different code rates or codeword lengths with a core for single instance use or smaller core for multiple instance use.  


Customize the solution to any 3D NAND flash memory or target application such as SATA and NVMe.


Scalability to match any throughput vs resource budgets.


Optimized solution for a specific FPGA or ASIC target.